The present invention relates generally to semiconductor integrated circuits (IC) and, more particularly, to a delay locked loop (DLL) circuit included in a semiconductor IC.
A conventional semiconductor IC, such as synchronous dynamic random access memory (SDRAM), uses a clock signal to increase operational speed. For this, a semiconductor IC includes a clock buffer that buffers an externally input clock signal. In some cases, a semiconductor IC includes a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate an internal clock signal in which the phase difference between the internal clock signal and the external clock signal has been corrected.
A DLL circuit delays a reference clock signal output from a clock input buffer using a delay line. A delay time, which is the delay of the reference clock signal by the delay line, is determined based on the result of a comparison between the phase of the reference clock signal and the phase of a feedback clock signal. The feedback clock signal is generated by delaying the output clock signal of the delay line by a delay value acquired by modeling the amount of delay occurring when the clock signal output from the delay line is transmitted to a data input/output buffer. To model this delay, a replica delayer is provided in the DLL circuit. With such a configuration, the DLL circuit outputs a clock signal having a phase that is earlier than that of the external clock signal by a predetermined time. Accordingly, the data input/output buffer can perform a buffering operation by using an internal clock signal whose timing coincides with the external clock signal.
FIG. 1 is a timing diagram shown for illustrating the operation of a known DLL circuit.
When referring to FIG. 1, it is possible to realize the phase relationship between a reference clock signal ‘clk_ref’ and a feedback clock signal during an initial operation of the DLL circuit. Herein, the feedback clock signal is represented as a first feedback clock signal ‘clk_fb1’ when the initial delay value of the delay line is at a minimum value; and the feedback clock signal is represented as a second feedback clock signal ‘clk_fb2’ when the delay line in an initial stage has a predetermined delay value. Generally, the delay line of the DLL circuit does not set the initial delay value to the minimum value. This purpose of this is to prevent a locking operation from being interrupted when the delay line must reduce the delay time after the initial operation. Typically, the initial delay value of the delay line of the DLL circuit is set to a delay amount that is half of the total delay amount of the delay line.
However, the second feedback clock signal ‘clk_fb2’ generated as a result of the predetermined initial delay value is also not synchronized with the first rising edge ‘RE1’ of the reference clock signal ‘clk_ref’; and therefore, the second feedback clock signal ‘clk_fb2’ must be synchronized with a second rising edge ‘RE2’. At this time, the total delay amount that the delay line must allocate to the reference clock signal ‘clk_ref’ for the locking operation exceeds one cycle of the reference clock signal ‘clk_ref’. Thus, when the delay line is initially set to be delayed by the predetermined initial delay value, the delay line must have a total delay amount that is larger than one cycle of the reference clock signal ‘clk_ref’. In actuality, the delay line is generally configured to have a total delay amount that is approximately two cycles against using a high-frequency clock signal.
Accordingly, the DLL circuit described above has limitations in that the length of the delay line increases. The length of the delay line has a problem not only in an area efficiency aspect, but also in that the length of the delay line causes an increase of an internal jitter component. Consequently, the operational stability of the above-described DLL circuit is reduced, thereby causing problems when attempting to realize high integration and increased speed of a semiconductor IC.